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Lin-analyzer

Abstract : The increasing complexity of FPGA-based accelerators, coupled with time-to-market pressure, makes high-level synthesis (HLS) an attractive solution to improve designer productivity by abstracting the programming effort above registertransfer level (RTL). HLS offers various architectural design options with different trade-offs via pragmas (loop unrolling, loop pipelining, array partitioning). However, non-negligible HLS runtime renders manual or automated HLS-based exhaustive architectural exploration practically infeasible. To address this challenge, we present Lin-Analyzer, a high-level accurate performance analysis tool that enables rapid design space exploration with various pragmas for FPGA-based accelerators without requiring RTL implementations.
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https://hal-uphf.archives-ouvertes.fr/hal-03383373
Contributor : Mylène Delrue Connect in order to contact the contributor
Submitted on : Monday, October 18, 2021 - 3:46:54 PM
Last modification on : Wednesday, November 3, 2021 - 9:06:42 AM

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Guanwen Zhong, Alok Prakash, Yun-Kuan Liang, Tulika Mitra, Smail Niar. Lin-analyzer. DAC '16: The 53rd Annual Design Automation Conference 2016, Jun 2016, Austin, Texas, United States. pp.1-6, ⟨10.1145/2897937.2898040⟩. ⟨hal-03383373⟩

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