Skip to Main content Skip to Navigation
Conference papers

Design Space exploration of FPGA-based accelerators with multi-level parallelism

Abstract : Applications containing compute-intensive kernels with nested loops can effectively leverage FPGAs to exploit fine-and coarse-grained parallelism. HLS tools used to translate these kernels from high-level languages (e.g., C/C--), however, are inefficient in exploiting multiple levels of parallelism automatically, thereby producing sub-optimal accelerators. Moreover, the large design space resulting from the various combinations of fineand coarse-grained parallelism options makes exhaustive design space exploration prohibitively time-consuming with HLS tools. Hence, we propose a rapid estimation framework, MPSeeker, to evaluate performance/area metrics of various accelerator options for an application at an early design phase. Experimental results show that MPSeeker can rapidly (in minutes) explore the complex design space and accurately estimate performance/area of various design points to identify the near-optimal (95.7% performance of the optimal on average) combination of parallelism options.
Document type :
Conference papers
Complete list of metadata
Contributor : Kathleen Torck Connect in order to contact the contributor
Submitted on : Wednesday, October 20, 2021 - 2:56:18 PM
Last modification on : Wednesday, November 3, 2021 - 4:45:36 AM




Guanwen Zhong, Alok Prakash, Siqi Wang, Yun-Kuan Liang, Tulika Mitra, et al.. Design Space exploration of FPGA-based accelerators with multi-level parallelism. IEEE/ACM Design Automation and Test in Europe (DATE'17), Mar 2017, Lausanne, Switzerland. pp.1141-1146, ⟨10.23919/DATE.2017.7927161⟩. ⟨hal-03388558⟩



Record views