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Framework for a Selection of Custom Instructions for Ht-MPSoC in Area-performance Aware Manner

Abstract : Using application-specific instructions for heterogeneous multiprocessor system-on-chip (Ht-MPSoC) allows to find a good performance/energy trade-off. For MPSoC architecture executing different multimedia applications, we expect a large number of potential custom instructions. In order to explore the potential of all these instructions, we propose to identify the similar critical computations to be executed on hardware accelerators (HWA) shared between processors. Depending on the running applications in one side and their needs in performance and area usage on the other side, private and shared hardware accelerators are attached to the different cores. This leads to a large architectural space exploration. In this letter we propose an FPGA-based framework capable of identifying the configuration of HWA targeted to an MPSoC architecture. Our framework incorporates a hardware accelerators sharing methodology to optimize area/performance tradeoff. The comparison of framework-estimated results and real measurements proves the efficiency of our framework.
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https://hal-uphf.archives-ouvertes.fr/hal-03401079
Contributor : Mylène Delrue Connect in order to contact the contributor
Submitted on : Monday, October 25, 2021 - 11:29:57 AM
Last modification on : Tuesday, October 26, 2021 - 4:00:32 AM

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Bouthaina Dammak Masmoudi, Mouna Baklouti, Rachid Benmansour, Smail Niar, Mohamed Abid. Framework for a Selection of Custom Instructions for Ht-MPSoC in Area-performance Aware Manner. IEEE Embedded Systems Letters, Institute of Electrical and Electronics Engineers, 2015, 7 (4), pp.105-108. ⟨10.1109/LES.2015.2461626⟩. ⟨hal-03401079⟩

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