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Conference papers

Optimization of matching and scheduling on heterogeneous CPU/FPGA architectures

Abstract : The continuous improvements in several application domains such as telecommunications, aerospace or multimedia lead to additional design constraints on power budget and architecture scalability. The heterogeneous CPU/FPGA (Central Processing Unit/Field-Programmable Gate Array) architecture is one of the most promising solutions in this context leading to high performance reconfigurable computing. In such systems, multi-core processors (CPU) provide high computation rates while the reconfigurable logic (FPGA) offers high performance and adaptability to the application real-time constraints. However, there is a lack of CAD (Computer Aided Design) tools able to deal with the development of applications on such heterogeneous systems. This research investigates the problem of the optimisation of static and run-time task mapping on a real-time computing system CPU/FPGA used to implement intimately coupled hardware and software models.
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https://hal-uphf.archives-ouvertes.fr/hal-03472671
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Submitted on : Thursday, December 9, 2021 - 2:31:55 PM
Last modification on : Friday, December 10, 2021 - 3:54:09 AM

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Omar Souissi, Rabie Ben Atitallah, David Duvivier, Abdelhakim Artiba. Optimization of matching and scheduling on heterogeneous CPU/FPGA architectures. 7th IFAC Conference on Manufacturing Modelling, Management, and Control, Jun 2013, Saint-Pétersbourg, Russia. pp.1678-1683, ⟨10.3182/20130619-3-RU-3018.00196⟩. ⟨hal-03472671⟩

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