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Shared Hardware Accelerator Architectures for Heterogeneous MPSoCs

Abstract : Heterogeneous Multiprocessor System-on-Chip (Ht-MPSoC) platforms are being increasingly deployed in high performance embedded systems. These architectures represent a promising alternative to homogeneous MPSoC architectures as they allow a higher performance energy trade-off. Ht-MPSoCs enhance the existing base instruction-set architecture (ISA) with application-specific custom instructions implemented on reconfigurable fabrics. However, the integration of a Ht-MPSoC with a high number of dedicated HW accelerators on a die may suffer from low area utilization. In this paper we propose a new architecture where Ht-MPSoC HW accelerators are shared among different processors in an intelligent manner. This paper demonstrates the feasibility of the approach on reconfigurable FPGA-based platforms. Experimental results on reconfigurable logic show that this approach reduces both application execution time, energy consumption and the required hardware resources
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https://hal-uphf.archives-ouvertes.fr/hal-03524974
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Submitted on : Thursday, January 13, 2022 - 3:38:54 PM
Last modification on : Wednesday, March 16, 2022 - 3:36:17 PM

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Bouthaina Dammak Masmoudi, Mouna Baklouti, Smail Niar, Mohamed Abid. Shared Hardware Accelerator Architectures for Heterogeneous MPSoCs. 8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip RecoSoc, Jul 2013, Darmstadt, Germany. ⟨10.1109/ReCoSoC.2013.6581549⟩. ⟨hal-03524974⟩

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