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Application specific multi-port memory customization in FPGAs

Abstract : FPGA block RAMs (BRAMs) offer speed advantages compared to LUT-based memory designs but a BRAM has only one read and one write port. Designers need to use multiple BRAMs in order to create multi-port memory structures which are more difficult than designing with LUT-based multiport memories. Multi-port memory designs increase overall performance but comes with area cost. In this paper, we present a fully automated methodology that tailors our multi-port memory from a given application. We present our performance improvements and area tradeoffs on state-of-the-art string matching algorithms.
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Submitted on : Tuesday, May 10, 2022 - 11:10:44 AM
Last modification on : Monday, May 16, 2022 - 1:11:11 PM


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Gorker Alp Malazgirt, Hasan Erdem Yantir, Arda Yurdakul, Smail Niar. Application specific multi-port memory customization in FPGAs. 24th International Conference on Field Programmable Logic and Applications (FPL) 2014, Sep 2014, Munich, Germany. pp.1-4, ⟨10.1109/FPL.2014.6927426⟩. ⟨hal-03663490⟩



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