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Accélération de la simulation par échantillonnage dans les architectures multiprocesseurs embarquées

Abstract : Embedded system design relies heavily on simulation to evaluate and validate new platforms before implementation. Nevertheless, as technological advances allow the realization of more complex circuits, simulation time of these systems is considerably increasing. This problem arises mostly in the case of embedded multiprocessor architectures (MPSoC) which offer high performances (in terms of instructions/Joule) but which require powerful simulators. For such systems, simultion should be accelerated in order to speed up their design flow thus reducing the time-to-market. In this thesis, we proposed a series of solutions aiming at accelerating the simulation of MPSoC. The proposed methods are based on application sampling. Thus, the parallel applications are first analyzed in order to detect the different phases which compose them. Thereafter and during the simulation, the phases executed in parallel are combined together in order to generate clusters of phases. We developed techniques that facilitate generating clusters, detecting repeated ones and recording their statistics in an efficient way. Each cluster represents a sample of similar execution intervals of the application. The detection of these similar intervals saves us simulating several times the same sample. To reduce the number of clusters in the applications and to increase the occurrence number of simulated clusters, an optimization of the method was proposed to dynamically adapt phase size of the applications. This makes it possible to easily detect the scenarios of the executed clusters when a repetition in the behavior of the applications takes place. Finally, to make our methodology viable in an MPSoC design environment, we proposed efficient techniques to construct the real system state at the simulation starting point (checkpoint) of the cluster.
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https://hal-uphf.archives-ouvertes.fr/tel-03032850
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Submitted on : Tuesday, December 1, 2020 - 9:46:32 AM
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Melhem Tawk. Accélération de la simulation par échantillonnage dans les architectures multiprocesseurs embarquées. Informatique [cs]. Université de Valenciennes et du Hainaut-Cambrésis, 2009. Français. ⟨NNT : 2009VALE0018⟩. ⟨tel-03032850⟩

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