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Gestion de la cohérence des données dans les systèmes multiprocesseurs sur puce

Abstract : The work presented in this thesis aims to provide an efficient hardware solution for managing cache coherency of shared data in shared memory multiprocessor systems-on-chip (MPSoC) dedicated for intensive signal processing applications. Several solutions are proposed in the literature to solve this problem. However, most of these solutions are efficient only for high-performance multiprocessor systems. These systems take rarely into account hardware resources and energy consumption limitations. In MPSoCs architectures these constraints are very important. In addition, these solutions do not take into account access patterns from the different processors to shared data. In this thesis, we propose a new approach for treating cache coherency problem. It consists on a new hybrid (invalidation/update) adaptive cache coherence protocol. A hardware architecture that facilitates its implementation and optimizes its performance is also proposed. The experimental results show that the proposed protocol in conjunction with this architecture provides an interesting level of performances and energy consumption.
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Submitted on : Friday, November 5, 2021 - 10:51:42 AM
Last modification on : Tuesday, November 23, 2021 - 9:45:20 AM
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  • HAL Id : tel-03416275, version 1


Hajer Chtioui. Gestion de la cohérence des données dans les systèmes multiprocesseurs sur puce. Informatique [cs]. Université de Valenciennes et du Hainaut-Cambrésis, 2011. Français. ⟨NNT : 2011VALE0036⟩. ⟨tel-03416275⟩



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