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Optimisation des performances et de la consommation de puissance électrique pour architecture Intel ltanium/EPIC

Abstract : This thesis proposes, in its first part, to extend the EPIC architecture of the Itanium processor family by providing a hardware stack. The principal idea defended here is that it is possible to close the existing performance gap between generic architectures and application specific designs to run virtual machines (FORTH, .NET, Java, etc). With this intention, we propose to reallocate dynamically a subset of the EPIC architecture’s resources to implement a hardware evaluation stack. Two implementations are proposed, both non-intrusive and compatible with existing binary codes. The fundamental difference between these stacks lies in their manager: software or hardware. The hardware controlled evaluation stack offers support for advanced functions such as the support of strongly typed evaluation stacks required by .NET’s CIL. Thus, we propose a single pass CIL binary translator into EPIC binary, using the hardware evaluation stack. In the second part of this thesis, we studied the energy efficiency of software applications. First, we defined a methodology and developed tools to measure the energy consumption and the useful work provided by the software. In a second time, we engaged the study of source code transformation rules in order to reduce/control the quantity of consumed energy by the software.
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Submitted on : Wednesday, November 18, 2020 - 3:28:58 PM
Last modification on : Tuesday, November 23, 2021 - 9:45:00 AM
Long-term archiving on: : Friday, February 19, 2021 - 8:03:35 PM


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  • HAL Id : tel-03012450, version 1


Jamel Tayeb. Optimisation des performances et de la consommation de puissance électrique pour architecture Intel ltanium/EPIC. Informatique [cs]. Université de Valenciennes et du Hainaut-Cambrésis, 2008. Français. ⟨NNT : 2008VALE0037⟩. ⟨tel-03012450⟩



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